In the sub-100 nm generation of integrated circuits (“ICs”), it is anticipated that copper (“Cu”) will replace aluminum as the new interconnect material due to its favorable electrical conductivity (1.67 μΩ.cm vs. 2.66 μΩ.cm of aluminum) and its superior resistance to electromigration. Additionally, improved electromigration resistance allows integrated circuits to operate at higher current densities and possibly at higher temperatures. IC chips fabricated with more conductive Cu interconnects and low-k dielectrics operate with less power and at significantly higher speed due to decreases in the interconnect RC coupling delay. The new dual-damascene patterning process coupling with chemical-mechanical planarization (CMP) significantly simplifies Cu interconnect routing and lowers manufacturing costs.
However, copper diffuses easily into active silicon devices and interlayer dielectrics (“ILD”), especially under electrical and thermal stresses resulting in deep level traps in the Si band gap. To prevent catastrophic contamination caused by Cu diffusion, diffusion barriers like tantalum (“Ta”) and tantalum nitride (“TaN”) are currently deposited in the damascene trench/via features by physical vapor deposition (PVD) to contain Cu interconnects. Since thin barrier layers of Ta (13.2 μΩ.cm) and TaN (>200 μΩ.cm) are too resistive to plate Cu directly, a continuous Cu-seeding layer (>7.5 nm) must be deposited over the Ta/TaN barrier to assure a good Cu electrofill.
The most challenging aspect of implementing Cu interconnects for advanced complementary metal-oxide-semiconductor (“CMOS”) applications beyond the 100 nm mode is the increasing difficulty with the overall process integration. Shrinking dimensions demand an increasingly high-aspect-ratio of trench/via features that make PVD barrier/seed deposition and Cu electrofill more difficult. The space situation is most severe at the bottom metallization layer where the first connections to sub-100 nm transistor array are made. For the future 45–65 nm CMOS devices, the thickness of a functional diffusion barrier is limited to merely 5 nm at this crucial metal layer. The current Cu/Ta/TaN stack approach can not be scaled down to meet the future industry roadmap requirements. In addition, any discontinuities in the Cu seed layer, large overhang, or poor coverage on the lower sidewall can affect the Cu electroplating through an early pinch-off of the structure, resulting in a void defect being formed. Structural integrity concerns and adhesion issues of the barrier metal to the new ultra low-k dielectric are often mentioned as accompanying problems.
The present invention greatly reduces the overall integration difficulties by replacing the current Cu Seed/Ta/TaN trilayer barrier configuration with a directly Cu-plate-able barrier layer consisting of a combination of Ruthenium (“Ru”) and Iridium (“Ir”) and their conductive oxides Ruthenium Oxide (“RuO2”) and Iridium Oxide (“IrO2”). The exact lateral chemical composition of this novel (Ru, RuO2) and/or (Ir, IrO2) diffusion barrier can be fine tuned to achieve strong adhesion between Cu/(Ru, RuO2)/interlayer dielectrics. With the new directly Cu-plate-able diffusion barrier, the costly Cu-seed layer can be eliminated which will greatly decrease copper interconnect processing costs and further simplifying circuit design and promoting overall integration success.